This invention relates generally to a process for forming dielectrically isolated substrates, and more specifically to a process for forming dielectrically isolated substrates having controlled thickness and doping concentration and to a process for using such substrates in the fabrication of dielectrically isolated semiconductor devices.
Dielectrically isolated devices in which a layer of dielectric material, usually oxide, surrounds the edges and bottom of a semiconductor island, isolating it from adjacent semiconductor islands, are used for circuit applications requiring a high degree of electrical isolation between circuit components. Dielectrically isolated circuits are used, for example, where the circuit will be subjected to a radiation environment, where interdevice leakages must be kept very small, where parasitic coupling between devices must be minimized, or where individual devices may have to withstand high applied voltages. The technique of dielectric isolation between devices is used in those applications in which more isolation is required than can be achieved with junction isolation.
Dielectrically isolated circuit fabrication has generally been low yielding because of the process by which the dielectrically isolated substrates are obtained. The conventional dielectric isolation process begins with a single crystal silicon wafer of the resistivity and doping type necessary for fabricating the intended semiconductor devices. For example, the starting wafer is typically selected to form the collector region of bipolar transistors or the body region of MOS transistors to be used in the circuit. A heavily doped buried layer region is then formed on the wafer and grooves are etched into the wafer surface to separate device regions. The surface of the wafer including the grooves is oxidized and a thick layer of polycrystalline silicon is deposited on the oxide. Then, in a most critical step, most of the starting wafer is lapped away to leave only a thin layer of the starting material. This step required lapping away as much as 750-1000 microns of silicon to leave a layer only 1-5 microns in thickness. The shaping tolerance required in this operation results in a very low process yield. Typically the remaining silicon left after the lapping operation varies in thickness across a wafer so that the layer is too thick in some places and too thin or even nonexistant in other places. For bipolar transistors, the circuit result of this is that some transistors on a wafer have too high a collector resistance, some are not isolated from adjoining devices, and others are subject to a low breakdown voltage because of the thin collector region.
Attempts have been made to produce dielectrically isolated structures by a process which does not rely on a shaping operation to control critical thicknesses. One such attempt is disclosed in U.S. Pat. No. 3,587,166 and subsquently reported by Davidsohn et al. in an article entitled "Dielectric Isolated Integrated Circuit Substrate Processes", Proceedings of the IEEE, Vol. 57, September, 1969, pages 1532-1537. In the process disclosed, the shaping operation is relatively noncritical. The shaped substrate is masked with a patterned oxide mask, etched, an then refilled with epitaxial material. Unfortunately, growing high quality epitaxial material is difficult on the etched substrate. Difficulites include those inherent in epitaxial growth in small apertures in addition to the formation of an irregular disordered region at the edges of the oxide aperture. The latter results, in part, from an oxide lip which overhangs the etched region of the substrate.
The growth of epitaxial material in the etched regions also results in the deposition of polycrystalline material over the masking oxide. This polycrystalline material must be removed by lapping. Ultimately, therefore, the thickness of the resulting structure depends on both an etching step and on a lapping step. The tolerance of either of these limiting steps can easily exceed the permissible tolerances on layer thickness. Any lapping leads to nonuniformities across a wafer, especially on a wafer having a patterned oxide on the surface. The oxide is more resistance than the semiconductor material and causes a scouring or dishing of the semiconductor material.
Because of the many potential applications for dielectrically isolated circuits and for the need to reduce the cost of the circuits, a need existed for a process which would provide high yielding dielectrically isolated substrates and circuits fabricated on those substrates.
It is therefore an object of this invention to provide an improved process for controllably fabricating dielectrically isolated semiconductor regions.
It is another object of this invention to provide an improved process for fabricating dielectrically isolated circuit structures.